Design of a First-Order Delta-Sigma Oversampling Modulator with Noise Constraints

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Alfred University. Faculty of Ceramic Engineering. Kazuo Inamori School of Engineering
In this thesis, a low noise, first-order, delta-sigma analog to digital modulator (ΣΔM) has been designed using a standard 0.5um CMOS process. The modulator is an amalgam of several other circuits including a folded-cascode transconductance amplifier, a latched comparator, a switched capacitor filter and a digital to analog converter (D/A). In each case, Tanner ToolsTM software was used to generate the circuit schematic and layout. In addition, the TannerTM package was used for the simulation and verification of all circuits. The ΣΔM was created using an approach that greatly speeds up the design, layout and verification process. Instead of using a conventional layout approach that requires each transistor to be individually designed, pre-drawn transistor pairs were implemented and wired to form the completed circuit. This approach allows complex circuits to be realized quickly. In addition, since all transistors used in the circuit layout originate from one or two transistor pairs, this approach greatly simplifies the verification process. Prior to the design of the ΣΔM, the Tanner ToolsTM suite was updated from a 1.6um technology to a newer and smaller 0.5um minimum feature size. This report details much of the work that was required to complete the transition from the old process to the new process. Moreover, several parts of the ΣΔM were scaled from the 1.6um minimum feature size to the newer, 0.5um technology. Two chips are currently being fabricated by the MOSIS service using 0.5um technology. The first design contains several individually wired parts of the ΣΔM. This chip will allow each part of the ΣΔM to be tested individually in the event to the ΣΔM does not perform as expected. The second design contains a complete ΣΔM that is wired on-chip. This design will allow the ΣΔM to be tested as a whole to verify its correct operation. This report will show through simulation that in most cases, the newer 0.5um designs were able to achieve higher gain and switch more quickly. Each circuit was simulated using 1.6um and 0.5um process parameters that were supplied by the MOSIS service. Furthermore, the simulations will show the operating potential of the completed ΣΔM.
Noise, Design, Oversampling, Modulation